Computers are nowadays often used in application areas which require reaction within a specified time interval. These are referred to as real-time systems. In such systems, the computers can be integrated as "embedded systems" into the application or can be implemented separately therefrom, for example, as memory-programmable controllers or automation computers. Such applications require uninterrupted operation (high-availability systems or H systems). In other uses, in the event of a fault the controlled system must not be placed in a state which is critical for safety and which leads to human life or valuable objects being put at risk (failsafe systems or F systems). Both arrangements can also occur simultaneously (H+F systems).
In all three aforementioned modes of operation it is necessary for the computer to have possible ways of conducting self tests during ongoing operation. As a result, faults which occur can be localized and faulty components can possibly be detected even before they bring about a faulty state of the system. The computer components which are most at risk are those with most transistors, that is to say memories, processors and peripheral logic.
In computers in which a plurality of Mbytes of memory are used, the memory contains the most transistors and thus constitutes the most important component to be tested.
A distinction is made between three logical fault classes: stuck-at faults, connection faults and pattern-sensitive faults (DIN V VDE 0801/A1: 1994-10. Grundsatze fur Rechner in Systemen mit Sicherheitsaufgaben (Principles for computers in systems with safety functions)). Depending on the degree to which these faults are discovered, a certain degree of effectiveness is allocated to the memory tests. In order to achieve a high level of effectiveness of a test, all the stuck-at faults, most of the connection faults and a large number of pattern-sensitive faults must be detected.
It is known that the test with the lowest level of complexity, and thus the shortest it execution time, is the test by Nair, Thatte and Abraham (R. Nair, S. M. Thatte, J. A. Abraham, Efficient Algorithms for Testing Semiconductor Random-Access Memories. IEEE Trans. on Comp. C-27, 6 (1978) 572-576), known as the Nair test for short.
In addition, Franklin tests (M. Franklin, K. K. Saluja, Hypergraph Coloring and Reconfigured RAM Testing, IEEE Trans. on Comp. 43, 6 (1994) 725-736; and M. Franklin, K. K. Saluja, An Algorithm to Test Reconfigured RAMS, 7th Intl. Conf. on VLSI Design, Calcutta, India, 5-8 Jan. 1994, Comp. Soc. Press (1994) 359-364), are known, which detect important pattern-sensitive faults even better than the Nair test when there is a relatively large amount of complexity with a high level of component integration. The Franklin tests can be considered as a logical extension of the Nair test, since they discover any triple fault, while the Nair test discovers only those triple faults in which all the memory cells involved are disjunctive. Thus, the Franklin tests, like the Nair test, can be classified as highly effective. All these tests have in common the fact that they do not require any knowledge of the physical cell architecture on the chip. The customary manufacturer's information is sufficient for correct execution.
Methods for testing a memory chip during ongoing operation are known from (D. Rhein, H. Freitag: Mikroelektronische Speicher (Microelectronic memories), SpringerVerlag Vienna, N. Y. 1992) and are designated in (D. Rhein, H. Freitag: Mikroelektronische Speicher (Microelectronic memories), Springer-Verlag Vienna, N.Y. 1992) as real-time data protection measures.
A method for testing a memory chip divided into cell arrays is known from (German Patent 40 11 987 C2). The memory chip in the known method is divided, in accordance with a matrix, into row areas and column areas (see FIG. 1).